R&D Engineering, Staff Engineer (VIP Verification)

Company: Synopsys, Inc.
Location: Sunnyvale
Posted on: April 4, 2025

Job Description:

Job Requirements

• Experience: 7 to 12 years
• Expertise: UVM and System Verilog
• Verification IP Modelling: Experience in verification IP modelling with knowledge of test case coding, scoreboard design, assertions, checkers & functional coverage.
• Development Experience: Involved & played a driving role in the development of reusable Verification environments for at least 2 verification projects using VMM/OVM/UVM methodologies.
• Protocol Experience: Should have experience on UCIe/PCIe/CXL/Unipro/USB/MIPI/HDMI/Ethernet/DDR/LPDDR/HBM memory protocol.Job Responsibilities
  • Able to contribute to the development of the VIP.
  • Responsible & can be relied on for review sign-off of VIP development and updates from a technical perspective including methodology and protocol functional perspective.
  • Liaison with Architects/methodology experts to achieve resolutions on issues or driving output from an architecture/methodology perspective.
  • Locally should be the 'go-to' person on all technical aspects of VIP.
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Keywords: Synopsys, Inc., Hayward , R&D Engineering, Staff Engineer (VIP Verification), Engineering , Sunnyvale, California